Many electronic systems are implemented using integrated circuits of different logic families. For example, computer systems often use complementary metal-oxide-semiconductor (“CMOS”) circuits to perform computational functions, low voltage differential signaling (“LVDS”) circuits for disk drive data signals, and positive emitter-coupled logic (“PECL”) circuits for clock drivers. These logic circuits are typically incompatible with each other in the sense that voltage levels specified for circuits of one logic family do not fall within the voltage range specified for circuits of a different logic family. Hence, data is lost or noise immunity is substantially impaired. For this reason, a receiver-translator circuit often is used to translate between signals of different logic families.
In addition to interfacing different logic families with each other, it may be desirable to interface different systems with each other. For example, many applications it is desirable to have a microprocessor capable of transmitting data to and receiving data from a multimedia card (MMC), or to have a microprocessor capable of transmitting data to and receiving data from a secure digital input/output (SDIO) system, or to have a microprocessor capable of transmitting data to and receiving data from a plurality of systems such as an MMC and an SDIO system. The microprocessor is also referred to as a central processing unit. Thus, the microprocessor should be capable of operating with one or more systems having different voltage parameters than the microprocessor and with each other. Interfacing different logic circuits, different transceivers, and different systems requires the use of different discrete translators to allow communications between the different circuit components. For example, a system may include a multiplicity of discrete circuit components coupled to an input of a translator and a discrete circuit component coupled to the output of the translator where the discrete circuit component coupled to the output of the translator has a different operating voltage than one or more of the circuit components connected to the input of the translator. This results in a higher system cost because of the need to inventory multiple translators and, since fewer translators of each type are used, the lack of economies of scale.
In addition to a higher cost, systems that include components that operate at different voltages may require additional circuitry to overcome incompatible supply voltage levels or may be limited in the acceptable supply voltages. For example, FIG. 1 illustrates a prior art logic voltage translator 10 used in a multiplexing application in which a plurality of circuits coupled to the inputs of the translator are limited to having the same voltage supply levels. What is shown in FIG. 1 is an n-channel pass transistor 12 coupled to p-channel edge-adjusting transistors 14 and 20 through corresponding one-shots 16 and 22, respectively. Pull-up resistors 18 and 24 are connected to p-channel edge-adjusting transistors 14 and 20, respectively. More particularly, n-channel pass transistor 12 has a source connected to an input/output node 26, a drain connected to an input/output node 28 and a gate coupled for receiving a source of operating potential VCC1. The drain of pass transistor 12 is coupled to the gate of edge-adjusting transistor 14 through one-shot 16 and the source of pass transistor 12 is coupled to the gate of edge-adjusting transistor 20 through one-shot 22. The source of pass transistor 12 is connected to a drain of edge-adjusting transistor 14 and to a terminal 19 of pull-up resistor 18 and the drain of pass transistor 12 is connected to a drain of edge-adjusting transistor 20 and to a terminal 25 of pull-up resistor 24. The gate of pass transistor 12 is connected to the source of edge-adjusting transistor 14 and to a terminal 21 of pull-up resistor 18. The source of edge-adjusting transistor 20 is connected to a terminal 27 of pull-up resistor 24 and, along with terminal 27, it is coupled for receiving a source of operating potential VCC2. A source-to-body diode 13 is formed between the source and drain of pass transistor 12.
The source of pass transistor 12, the drain of edge-adjusting transistor 14, and terminal 19 of pull-up resistor 18 are commonly connected together and to input/output node 26 and the drain of edge-adjusting transistor 20 and terminal 25 of pull-up resistor 24 are commonly connected together and to input/output node 28.
Transceivers 301, 302, . . . , 30n are connected to logic translator 10. Each transceiver 301, 302, . . . , 30n includes input/output transistors 321, 322, . . . , 32n and input/output buffers 341, 342, . . . , 34n, wherein the drains of input/output transistors 321, 322, . . . , 32n and the input terminals of input/output buffers 341, 342, . . . , 34n are connected to input/output nodes 311, 312, . . . , 31n, respectively. Each transceiver 301, 302, . . . , 30n is coupled for receiving source of operating potential VCC1. The gates of input/output transistors 321, 322, . . . , 32n are connected to control circuits 361, 362, . . . , 36n, the sources of input/output transistors 321, 322, . . . , 32n are coupled for receiving a source of operating potential VSS1, and the output terminals of input/output buffers 341, 342, . . . , 34n are connected to logic circuits 381, 382, . . . , 38n, respectively. By way of example, source of operating potential VSS1 is ground. It should be noted that for purposes of clarity, control circuits 361, 362, . . . , 36n and logic circuits 381, 382, . . . , 38n are shown in block form and that the types of control and logic circuits are known to those skilled in the art. Input/output nodes 311, 312, . . . , 31n of transceivers 301, 302, . . . , 30n are connected to input/output node 26 of logic voltage translator 10.
A transceiver 40 is connected to input/output node 28 of logic voltage translator 10. Transceiver 40 includes an input/output transistor 42 and an input/output buffer 44 wherein a drain of input/output transistor 42 and an input terminal of input/output buffer 44 are connected to input/output node 56 which in turn is connected to input/output node 28. Transceiver 40 is coupled for receiving source of operating potential VCC2. The gate of input/output transistor 42 is connected to a control circuit 46, the source of input/output transistor 42 is coupled for receiving a source of operating potential VSS2, and the output terminal of input/output buffer 44 is connected to a logic circuit 48. By way of example, source of operating potential VSS2 is ground. For purposes of clarity, control circuit 46 and logic circuit 48 are shown in block form. The types of control and logic circuits are known to those skilled in the art.
Before describing the operation of logic voltage translator 10, it should be noted that for the sake of explaining its operation, supply voltage VCC2 is assumed to be greater than supply voltage VCC1 which is assumed to be greater than the threshold voltage of pass transistor 12. However, supply voltage VCC1 may be greater than, less than, or equal to supply voltage VCC2. Furthermore, the supply voltages VCC1 for each transceiver 301, 302, . . . , 30n are the same. A logic low or logic zero voltage is transmitted to transceiver 40 by turning on one of input/output transistors 321, 322, . . . , 32n of a selected transceiver 301, 302, . . . , 30n. Techniques for selecting a transceiver from a plurality of transceivers are known to those skilled in the art. Turning on one of input/output transistors 321, 322, . . . , 32n sets the voltage at the corresponding input/output node 311, 312, . . . , 31n to a logic low or a logic zero voltage level, which is transmitted to input/output node 26. The logic low voltage appearing at input/output node 26 sets the gate-to-source voltage of pass transistor 12 to be approximately equal to supply voltage VCC1. Thus, pass transistor 12 turns on, setting the voltage at input/output node 28 equal to a logic zero voltage, e.g., equal to approximately zero volts.
Transceiver 40 transmits a logic zero voltage to the selected transceiver 301, 302, . . . , 30n by turning on input/output transistor 42, which sets the voltage at input/output node 56 to a logic low or logic zero voltage. The logic zero voltage on input/output node 56 is transmitted to input/output node 28 causing body diode 13 to become forward biased, turning on pass transistor 12 and producing a logic zero voltage at input/output node 26.
A logic high or logic one voltage is transmitted from input/output node 26 to input/output node 28 or from input/output node 28 to input/output node 26 by turning off input/output transistors 321, 322, . . . , 32n and input/output transistor 42. Turning off input/output transistors 321, 322, . . . , 32n and input/output transistor 42 sets the gate-to-source voltage of pass transistor 12 to approximately zero volts, thereby turning off pass transistor 12. Because pass transistor 12 is off, the voltages appearing at input/output nodes 26 and 28 are equal to supply voltages VCC1 and VCC2, respectively. A disadvantage with logic translator 10 is that a voltage VCC1 appearing at input/output node 26 may exceed the maximum operating voltage of transceiver modules 301, 302, . . . , 30n causing an increased power consumption and eventually damaging one or more of them. Another disadvantage with logic translator 10 is that supply voltages VCC1 for each transceiver 301, 302, . . . , 30n are the same.
Accordingly, it would be advantageous to have a structure and method for multiplexing and translating at least one of a plurality of electrical signals or demultiplexing at least one of the plurality of electrical signals. It would be of further advantage for the structure and method to be cost efficient.